Chapter 1

Prelude - Chapter 1 - Chapter 2 - Chapter 3 - Chapter 4 - Chapter 5 - Chapter 6 - Chapter 7

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Table of Contents

Chapter 1

Basic pipelining and simple RISC processors

The ten most frequently used instructions in the SPECint92 for Intel x86

RISC movement in processor architecture

Instruction Set Architecture (ISA)

ISA - Processor architecture - Microarchitecture

How is data represented? - Data formats

Where can data be stored? - Address space

How can data be accessed? - Addressing modes

Addressing modes (continued)

Addressing modes

RISC addressing modes

What operations can be done on data? - Instruction set

Instruction set (continued)

Instruction set (continued)


How are instructions encoded? - Instruction and addressing formats


Examples of RISC ISAs: MIPS II

Examples of RISC ISAs: DEC Alpha

Basic RISC design principles

Datapath organization of a simple RISC processor

Pipelining definitions

Speedup assumptions

The base pipeline is the most simple DLX RISC pipeline

Basic pipeline steps

Basic Pipeline Steps (continued)

Pipeline (1)

Pipeline (2)

Pipeline (3)

Pipeline (4)

Pipeline (Overview)


Pipelining hazards and solutions - Three types of pipeline hazards


Data Hazards

Data hazards in an instruction pipeline

WAR and WAW: can they happen in our pipeline?

Pipeline conflict due to a data hazard

Solutions for data hazards from true data dependences

Data hazard: Hardware solution by interlocking

Data hazard: Hardware solution by forwarding

Pipeline hazard due to data dependence unresolvable by forwarding

Unremovable pipeline bubble due to data dependence

Structural Hazards

Pipeline bubble due to a structural hazard

Solutions to the structural hazard

Control Hazards, delayed branch technique, and static branch prediction

Bubbles after a taken branch

Solution: Decide branch direction earlier

Solution: Calculation of the branch direction and of the branch target address in ID stage

Software Solution

Hardware solution - Interlocking

Static branch prediction

Static branch prediction - Machine-fixed

Static branch prediction - Compiler-based

Hardware solutions: BTAC

BTAC (continued)

BTB (Branch target buffer)

Multiple-cycle operations and out-of-order execution

Example of a WAW hazard caused by a long-latency operation and out-of-order completion

Solutions to the problem of multiple-cycle operations

WAR possible?

Pipelining basics: summary

RISC Processors: Early RISC Processors

Case study: MIPS R3000

Case Study: MIPS R3000

Case Study: MIPS R4000 (and R4400)

Performance of the MIPS R4000 pipeline

Java-processors overview

Stack architecture: Java Virtual Machine

Case study: picoJava-I (and microJava 701)

picoJava-I microarchitecture

picoJava-I microarchitecture features

picoJava-I pipeline

picoJava-I stack architecture & drippler

JVM instruction frequencies

picoJava-I instruction set


JVM instruction frequencies without and with folding

microJava 701 preview

picoJava-I evaluation

The Komodo microcontroller: MT ("Multithreaded") Java core

Conclusions to Chapter 1

Author: Jurij Silc


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