n instructions execute in n*k cycles on a hypothetical non-pipelined processor with k stages,
the execution of n instructions on a k-stage pipeline will take k+n-1 cycles, assuming ideal conditions with latency k cycles and throughput 1.
Speedup = n*k / (k+n-1) = k / (k/n + 1 - 1/n)
Ideal speedup (n ? infinite) = k