Basic pipeline steps
Instruction fetch (IF): the instruction pointed to by the PC is fetched from memory into the instruction register of the CPU, and the PC is incremented to point to the next instruction in the memory.
Instruction decode/register fetch (ID): the instruction is decoded, and in the second half of the stage the operands are transferred from the register file into the ALU input registers (here meaning: latches).
Execution/effective address calculation (EX): the ALU operates on the operands from ALU input registers and eventually puts the result into ALU output register. The contents of this register depend on the type of instruction. If the instruction is:
- register-register (e.g. arithmetic/logical): the ALU outputs the result of the operation into the ALU output register;
- memory reference (e.g. load/store), the ALU output register contains an effective memory address;
- control transfer (e.g. branch on equal), then the ALU produces the jump / branch target address (which is stored in the ALU output register) and, at the same time, the branch direction.