The cycle time of the pipeline is dictated by the critical path: the slowest pipeline stage.
All stages use different CPU resources (no resource conflicts are possible in our simple but well-balanced pipeline!).
Ideally, each cycle another instruction is fetched, decoded, executed, etc. (CPI=1).
Pipeline hazards: phenomena that disrupt the smooth execution of a pipeline.
- If we assume a unified cache with a single read port (instead of separate I- and D-caches) ? a memory read conflict appears among IF and MEM stages.
- The pipeline has to stall one of the accesses until the required memory port is available.
A stall is also called a pipeline bubble.