Solutions for data hazards from true data dependences
Software solution (Compiler scheduling):
- Putting no-op instructions after each instruction that may cause a hazard
- Instruction scheduling: rearrange code to reduce no-ops
Hardware solutions: detect hazard!! Hazard detection logic necessary!
- Interlocking: stall pipeline for one or more cycles
- Forwarding: In our pipeline two types of forwarding:
- the result in ALU output of Instr1 in EX stage can immediately be forwarded back to ALU input of EX stage as an operand for Instr2,
- the load memory data register from MEM stage can be forwarded to ALU input of EX stage.
- Forwarding with interlocking: Assuming that Instr2 is data dependent on the load instruction Instr1 then Instr2 has to be stalled until the data loaded by Instr1 becomes available in the load memory data register in MEM stage. Even when forwarding is implemented from MEM back to EX, one bubble occurs that cannot be removed.