Problem (resource conflict): Structural hazards do not arise in our simple pipeline.
However, assume: the pipeline would be able to write back results of register-register instructions already in MEM stage (and not in WB stage):
- MEM stage would be able to write back an ALU output in case of a register-register instruction (from ALU output register) into a single-write-port register file.
- Consider a sequence of two instructions, Instr1 and Instr2, with Instr1 fetched before Instr2, and assume that Instr1 is a load, while Instr2 is a data independent register-register instruction.
- Due to memory addressing, the data loaded by Instr1 arrives at the register file write port at the same time as the result of Instr2, causing a resource conflict.