Solution: Calculation of the branch direction and of the branch target address in ID stage
However, then the ALU can no more be used for calculating the branch target address ? a structural hazard, which can be avoided by an additional ALU for the branch target address calculation in ID stage.
And a new unremovable pipeline hazard arises:
- An ALU instruction followed by an (indirect) branch on the result of the instruction will incur a data hazard stall even when the result value is forwarded from the EX to the ID stage (similar to the data hazard from a load with a succeeding ALU operation that needs the loaded value).
The main problem with this pipeline reorganization: decode, branch target address calculation, and PC write back within a single pipeline stage ? a critical path in the decode stage that reduces the cycle rate of the whole pipeline.
Assuming an additional ALU and a write back of the branch target address to the PC already in the ID stage, if the branch is taken, only a one cycle delay slot arises