Delayed jump / branch technique: The compiler fills the delay slot(s) with instructions that are in logical program order before the branch.
- The moved instructions within the slots are executed regardless of the branch outcome.
- The probability of:
- moving one instruction into the delay slot is greater than 60%,
- moving two instructions is 20%,
- moving three instructions is less than 10%.
The delayed branching was a popular technique in the first generations of scalar RISC processors, e.g. IBM 801, MIPS, RISC I, SPARC.
In superscalar processors, the delayed branch technique complicates the instruction issue logic and the implementation of precise interrupts. However, due to compatibility reasons it is still often in the ISA of some of today's microprocessors, as e.g. SPARC- or MIPS-based processors.