Solutions to the problem of multiple-cycle operations
Interlocking: stall Inst2 in the pipeline until Inst1 leaves the EX stage ? pipeline bubbles, slow down
A single pipelined FU: general-purpose FU for all kind of instructions ? slows down execution of simple operations
Multiple FUs: Inst2 may proceed to some other FU and overlap its EX stage with the EX stage of Inst1
- ? out-of-order execution!
- instructions complete out of the original program order
- WAW hazard caused by output dependence may occur ? delaying write back of second operation solves WAW hazard ? further solutions: scoreboarding, Tomasulo, reorder buffer in superscalar
Solutions in the example
- delay mul instruction until div instruction has written its result
- write back result of mul instruction and purge result of div ? question: precise interrupt in case of division by zero ?