Case Study: MIPS R4000 (and R4400)
8 Stage Pipeline (sometimes called: superpipeline):
- IF: first half of fetching of instruction; PC selection, initiation of instruction cache access.
- IS: second half of access to instruction cache.
- RF: instruction decode and register fetch, hazard checking, and also instruction cache hit detection.
- EX: execution, which includes effective address calculation, ALU operation, and branch target computation and condition evaluation.
- DF: data fetch, first half of access to data cache.
- DS: second half of access to data cache.
- TC: tag check, determine whether the data cache access hit.
- WB: write back for loads and register-register operations.