Lessons learned from dataflow (Pipeline issues)
Microprocessors: Data and control dependences potentially cause pipeline hazards that are handled by complex forwarding logic.
Dataflow: Due to the continuous context switches, pipeline hazards are avoided; disadvantage: poor single thread performance.
Microprocessors: Antidependences and output dependences are removed by register renaming that maps the architectural registers to the physical registers.
Thereby the microprocessor internally generates an instruction stream that satisfies the single assignment rule of dataflow.
The main difference between the dependence graphs of dataflow and the code sequence in an instruction window of a microprocessor:branch prediction and speculative execution.
Microprocessors: rerolling execution in case of a wrongly predicted path is costly in terms of processor cycles.