Chapter 3

Prelude - Chapter 1 - Chapter 2 - Chapter 3 - Chapter 4 - Chapter 5 - Chapter 6 - Chapter 7


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Table of Contents

Chapter 3

CISC processors

Prerequisites for CISC processors

A brief look at CISC processors

Scheduling

Dynamic scheduling

Scoreboarding

Scoreboard pipeline

Scoreboarding

Scoreboarding (in more detail)

Scoreboard implementation

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

Scoreboarding example

CDC 6600 processor

CDC 6600 Processor

Scoreboard summary

Register renaming

Tomasulo algorithm

Tomasulo Organization

Reservation station components

Reservation station entries

Tomasulo organization

CBD and reservation stations

Three stages of Tomasulo algorithm

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Tomasulo scheduling

Comment on the original Tomasulo scheme

Tomasulo summary

IBM 360/91

IBM 360/91

IBM 360/91 implementation details

Lessons learned from CISC

Author: Jurij Silc

Email: Jurij.Silc@ijs.si

Home Page: http://www-csd.ijs.si/silc

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