Comment on the original Tomasulo scheme
In the original Tomasulo scheme, the CDB is reserved at least two cycles in advance
each instruction stays at least two cycles in the EX phase
CDB resource conflicts are solved at CDB reservation time (before execution)
In contrast, we assume CDB resource conflict resolution in WB stage (see cycle 6 in example).
What happens when an instruction is issued and one of its operands is on the CDB in the same cycle?
Uncertain in original Tomasulo paper! We assume the instruction snoops the CDB already in issue phase (see cycle 4 in example).