Belongs to the family of the IBM System/360 architecture which all share the ISA.
The IBM System/360 Model 91 was deeply pipelined (overall pipeline length was 20 stages).
Floating-point execution unit: two separate, fully pipelined floating-point FUs, the adder and the multiplier/divider. The FUs could be used concurrently.
Addition took two cycles, multiplication three cycles, and division eleven cycles.
Three reservation stations (RS) associated to adder, and two to the multiplier/divider.
A speculative branch prediction was used that speculated the target will be taken, when the branch target instruction is within the last eight instructions.
Memory had a 10-cycle access, it was fully buffered and 32-way interleaved. The processor could have up to 32 memory accesses pending to reduce latency.