Explanation of the term “superscalar”
Dynamic issue of superscalar processors can allow issue of instructions either in-order, or it can allow also an issue of instructions out of program order.
- Only in-order issue is possible with VLIW processors.
The dynamic instruction issue complicates the hardware scheduler of a superscalar processor if compared with a VLIW.
The scheduler complexity increases when multiple instructions are issued out-of-order from a large instruction window.
It is a presumption of superscalar that multiple FUs are available.
- The number of available FUs is at least the maximum issue bandwidth, but often higher to diminish potential resource conflicts.
The superscalar technique is a microarchitecture technique, not an architecture technique.