Temporal vs. spacial parallelism
Instruction pipelining, superscalar and VLIW techniques all exploit fine-grain (instruction-level) parallelism.
Pipelining utilizes temporal parallelism.
Superscalar and VLIW techniques utilize also spatial parallelism.
Performance can be increased by longer pipelines (deeper pipelining) and faster transistors (a faster clock) emphasizing an improved pipelining.
Provided that enough fine-grain parallelism is available, performance can also be increased by more FUs and a higher issue bandwidth using more transistors in the superscalar and VLIW cases.