High-bandwidth branch prediction
Future microprocessor will require more than one prediction per cycle starting speculation over multiple branches in a single cycle,
- e.g. Gag predictor is independent of branch address.
When multiple branches are predicted per cycle, then instructions must be fetched from multiple target addresses per cycle, complicating I-cache access.
- Possible solution: Trace cache in combination with next trace prediction.
Most likely a combination of branch handling techniques will be applied,
- e.g. a multi-hybrid branch predictor combined with support for context switching, indirect jumps, and interference handling.