Superscalar processor: In-order delivery of instructions to the out-of-order execution kernel!
- Fetch and decode instructions at a higher bandwidth than execute them.
- Delivery task: Keep instruction window kept full ? the deeper instruction look-ahead allows to find more instructions to issue to the execution units.
The processor fetches and decodes today about 1.4 to twice as many instructions than it commits (because of mispredicted branch paths).
Typically the decode bandwidth is the same as the instruction fetch bandwidth.
Multiple instruction fetch and decode is supported by a fixed instruction length.