Pentium II/III: The in-order section
The instruction fetch unit (IFU) accesses a non-blocking I-cache, it contains the Next IP unit.
The Next IP unit provides the I-cache index (based on inputs from the BTB), trap/interrupt status, and branch-misprediction indications from the integer FUs.
- two-level adaptive scheme of Yeh and Patt,
- BTB contains 512 entries, maintains branch history information and the predicted branch target address.
- Branch misprediction penalty: at least 11 cycles, on average 15 cycles
The instruction decoder unit (IDU) is composed of three separate decoders