Pentium II/III: The in-order section (Continued)
A decoder breaks the IA-32 instruction down to ?ops, each comprised of an opcode, two source and one destination operand. These ?ops are of fixed length.
- Most IA-32 instructions are converted directly into single micro ops (by any of the three decoders),
- some instructions are decoded into one-to-four ?ops (by the general decoder),
- more complex instructions are used as indices into the microcode instruction sequencer (MIS) which will generate the appropriate stream of ?ops.
The ?ops are send to the register alias table (RAT) where register renaming is performed, i.e., the logical IA-32 based register references are converted into references to physical registers.
Then, with added status information, ?ops continue to the reorder buffer (ROB, 40 entries) and to the reservation station unit (RSU, 20 entries).