VLIW (very long instruction word) processors use a long instruction word that contains a usually fixed number of operations that are fetched, decoded, issued, and executed synchronously.
All operations specified within a VLIW instruction must be independent of one another.
Some of the key issues of a (V)LIW processor:
- (very) long instruction word (up to 1 024 bits per instruction),
- each instruction consists of multiple independent parallel operations,
- each operation requires a statically known number of cycles to complete,
- a central controller that issues a long instruction word every cycle,
- multiple FUs connected through a global shared register file.