VLIW and superscalar
Sequential stream of long instruction words.
Instructions scheduled statically by the compiler.
Number of simultaneously issued instructions is fixed during compile-time.
Instruction issue is less complicated than in a superscalar processor.
Disadvantage: VLIW processors cannot react on dynamic events, e.g. cache misses, with the same flexibility like superscalars.
The number of instructions in a VLIW instruction word is usually fixed.
Padding VLIW instructions with no-ops is needed in case the full issue bandwidth is not be met. This increases code size. More recent VLIW architectures use a denser code format which allows to remove the no-ops.
VLIW is an architectural technique, whereas superscalar is a microarchitecture technique.
VLIW processors take advantage of spatial parallelism.