Architectural challenges and implications
Preserve object code compatibility (may be avoided by a virtual machine that targets run-time ISAs)
It is necessary to find ways of expressing and exposing more parallelism to the processor. It is doubtful if enough ILP is available.
Buses may probably scale. Expect much wider buses in future.
Memory bottleneck: Memory latency may be solved by a combination of technological improvements in memory chip technology and by applying advanced memory hierarchy techniques (other authors disagree).
Power consumption for mobile computers and appliances.
Soft errors by cosmic rays of gamma radiation may be faced with fault-tolerant design through the chip.