Future processors to use coarse-grain parallelism
Today‘s microprocessors utilize instruction level parallelism by a deep instruction pipeline and by the superscalar or VLIW multiple issue techniques
Today‘s (2001) technology: approx. 40 M transistors per chip, In future (2012): 1.4 G transistors per chip,What next?
- Increase of single-thread performance--> use of more speculative instruction-level parallelism
- Increase of multi-thread (multi-task) performance--> Utilize thread-level parallism additionally to instruction-level parallelismA „thread“ in this lecture means a „HW thread“ which can be a SW (Posix) thread, a process, ...
Far future (??): Increase of single-thread performance by use of speculative instruction-level and thread-level parallelism