Requirements and solution
Delivering optimal instruction bandwidth requires:
- a minimal number of empty fetch cycles,
- a very wide (conservatively 16 instructions, aggressively 32), full issue each cycle,
- and a minimal number of cycles in which the instructions fetched are subsequently discarded.
Consuming this instruction bandwidth requires:
- sufficient data supply,
- and sufficient processing resources to handle the instruction bandwidth.
- an instruction cache system (the I-cache) that provides for out-of-order fetch (fetch, decode, and issue in the presence of I-cache misses).
- a large Trace cache for providing a logically contiguous instruction stream,
- an aggressive Multi-Hybrid branch predictor (multiple, separate branch predictors, each tuned to a different class of branches) with support for context switching, indirect jumps, and interference handling.