Instruction supply and out-of-order fetch
An in-order fetch processor, upon encountering a trace cache miss, waits until the miss is serviced before fetching any new segments.
But an out-of-order fetch processor temporarily ignores the segment associated with the miss, attempting to fetch, decode, and issue the segments that follow it.
After the miss has been serviced, the processor decodes and issues the ignored segment.
Higher performance can be achieved by fetching instructions that—in terms of a dynamic instruction trace—appear after a mispredicted branch, but are not control-dependent upon that branch.
In the event of a mispredict, only instructions control-dependent on the mispredicted branch are discarded.
Out-of-order fetch provides a way to fetch control-independent instructions.