Proper resolution of inter-task data dependences
Concerns in particular data that is passed between instructions via registers and via memory.
To maintain a sequential appearance a twofold strategy is employed.
- First, each processing element adheres to sequential execution semantics for the task assigned to it.
- Second, a loose sequential order is enforced over the collection of processing elements, which in turn imposes a sequential order of the tasks.
The sequential order on the processing elements is maintained by organizing the elements into a circular queue.
The appearance of a single logical register file is maintained although copies are distributed to each parallel PE.
- Register results are dynamically routed among the many parallel processing elements with the help of compiler-generated masks.
For memory operations: An address resolution buffer (ARB) is provided to hold speculative memory operations and to detect violations of memory dependences.