Load access latencies measured on an Alpha Server 4100 SMP with four 300 MHz Alpha 21164 processors are:
- 7 cycles for a primary cache miss which hits in the on-chip L2 cache of the 21164 processor,
- 21 cycles for a L2 cache miss which hits in the L3 (board-level) cache,
- 80 cycles for a miss that is served by the memory, and
- 125 cycles for a dirty miss, i.e., a miss that has to be served from another processor's cache memory.
Multithreaded processors are able to bridge latencies by switching to another thread of control - in contrast to chip multiprocessors.