SMT at the Universities of Washington and San Diego
Hypothetical out-of-order issue superscalar microprocessor that resembles MIPS R10000 and HP PA-8000.
8 threads and 8-issue superscalar organization are assumed.
Eight instructions are decoded, renamed and fed to either the integer or floating-point instruction window.
When operands become available, up to 8 instructions are issued out-of-order per cycle, executed and retired.
Each thread can address 32 architectural integer (and floating-point) registers. These registers are renamed to a large physical register le of 356 physical registers.