Technological trends have produced a large and growing gap between processor speed and DRAM access latency.
Today, it takes dozens of cycles for data to travel between the CPU and main memory.
CPU-centric design philosophy has led to very complex superscalar processors with deep pipelines.
Much of this complexity is devoted to hiding memory access latency.
Memory wall: the phenomenon that access times are increasingly limiting system performance.
Memory-centric design is envisioned for the future!
PIM or Intelligent RAM merge processor and memory into a single chip.