Experiences with Sun's SPARCStation 5
- contains a single-scalar microSPARC processor with 16 kB I-cache and 16 kB D-cache on-chip and no secondary cache.
- Memory controller is integrated onto the processor chip, so that DRAM devices are driven directly by logic on the processor chip.
- comparable high-end machine of the same era, containing a superscalar SuperSPARC processor with separate 20 kB I-cache and 16 kB D-cache, and a shared secondary cache of 1 MB.
SPARCStation 5 has an inferior SPEC92-rating, yet it outperforms the SPARCStation 10/61 on a logic synthesis workload that has a working set of over 50 MB.
- Reason: the lower main memory latency of the SPARCStation 5, which compensates for the slower processor.
- Codes that frequently miss the SPARCStation 10's large secondary cache have lower access times on the SPARCStation 5.