Scaling a system beyond a single PIM.
- The amount of DRAM on a single PIM chip is bounded.
- The DRAM core will need more I/O lines which affects IRAM's cost per bit.
- Also refresh rate is affected.
The DRAM technology today does not allow on-chip coupling of high performance processors with DRAM memory since the clock rate of DRAM memory is too low.
- Logic and DRAM manufacturing processes are fundamentally different.
The PIM approach can be combined with most processor organizations.
- The processor(s) itself may be a simple or moderately superscalar standard processor,
- it may also include a vector unit as in the vector IRAM type,
- or be designed around a smart memory system, exemplified by the Active Page approach.
- In future: potentially memory-centric architectures.