Proposal: Vector IRAM
A scalar processor is combined with a vector unit and the memory system on a single die.
The vector unit contains vector registers and multiple parallel pipelines operating concurrently.
Potential configuration for 0.13 ?m, 400 mm2 die, 1 GHz:
- Vector unit: two load, one store, two arithmetic units.
- Dual-issue scalar core processor with first-level instruction and data cache.
- 96 Mbytes memory organized in 32 sections each comprising sixteen 1.5 Mbit banks and a crossbar-switch.
- Assuming pipelined synchronous-DRAM interface with 20-ns latency and 4 ns cycle time ? 192 Gbytes per second bandwidth to the vector unit.
- 16 GFLOPS peak.
Low-cost vector microprocessor for numerical problems but also for multimedia, database accesses, data mining, and many other applications.