The MorphoSys system
MorphoSys project at the University of California at Irvine
Goal: design and build a processor with an accompanying reconfigurable circuit chip which is tolerated to operate much slower than the processor.
Targeted at image processing applications.
It consists of
- a control processor with I-cache/D-cache,
- a reconfigurable array with an associated control memory,
- a data buffer (usually acting as a frame buffer),
- and a DMA controller.