Potential one-billion transistor configuration
Each tile uses 5 million transistors for memory:
- 16 Kbyte instruction memory (IMEM)
- 16 Kbyte switch instruction memory (SMEM)
- 32 Kbyte first-level data memory (DMEM)
Each tile uses 2 million transistors for CPU (R2000 equivalent) and configurable logic.
Switched interconnect between tiles instead of buses.
Two sets of control logic: operation control for processor and sequencing routing instructions for the static switch.
Multigranular operations: configurable logic in each tiles supports few wide-word or many narrow-word operations, coarser than FPGA-based processors.