Conclusions on Raw
RawLogic prototype (Sun SparcStation with FPGA-based logic emulation).
Compiler resembles more a hardware synthesis tool than a high-level language compiler
? very long compile-time (several hours).
The burden on the compiler is extreme, it is unclear how this complexity could be handled.
The approach is static; reaction to dynamic events is a draw-back.
Potentially 10 to 1000 speedup over Sparc 20/71 (calculated not measured!).