Current and Future Trends in Processor Architecture


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Table of Contents

Current and Future Trends in Processor Architecture

Tutorial Background Material

Outline of the Tutorial

Part I: State-of-the-art multiple-issue processors

Multiple-issue Processors

Instruction Pipelining

Superscalar Pipeline

Superscalar vs. VLIW

Sections of a Superscalar Pipeline

Components of a Superscalar Processor

Branch-Target Buffer or Branch-Target Address Cache

Branch Prediction

Misprediction Penalty

Static Branch Prediction

Dynamic Branch Prediction

One-bit Predictor

One-bit vs. Two-bit Predictors

Two-bit Predictors (Saturation Counter Scheme)

Two-bit Predictors (Hysteresis Scheme)

Two-bit Predictors

Two-bit Predictors and Correlation-based Prediction

Predictor Behavior in Example

Correlation-based Predictor

Correlation-based Prediction (2,2)-predictor

Two-level Adaptive Predictors

Implementation of a GAg(4)-predictor

Variations of Two-level Adaptive Predictors

Two-level Adaptive Predictors

gselect and gshare Predictors

Hybrid Predictors

Simulations of Grunwald 1998

Results

Confidence Estimation

Predicated Instructions

Predication Example

Predication

Eager (Multipath) Execution

Branch handling techniques and implementations

High-Bandwidth Branch Prediction

Back to the Superscalar Pipeline

Decode Stage

Decoding variable-length instructions

Two principal techniques to implement renaming

Issue and Dispatch

Issue

Reservation Station(s)

Dispatch

The following issue schemes are commonly used

Single-level, two-window issue

Two-level issue with multiple windows

Execution Stages

Types of FUs

Multimedia Units

Finalizing Pipelined Execution - Completion, Commitment

Finalizing Pipelined Execution - Retirement and Write-Back

Reorder Buffers

Precise Interrupt (Precise Exception)

VLIW and EPIC

Intel's IA-64 EPIC Format

Part II: Microarchitectural solutions for future microprocessors

Technological Forecasts

Design Challenges

Architectural Challenges and Implications

Future Processor Architecture Principles

Processor Techniques to Speed-up Single-threaded Application

Advanced Superscalar Processors for Billion Transistor Chips

The Trace Cache

I-cache and Trace Cache

Superspeculative Processors

Strong- vs. Weak-dependence Model

Implementation of a Weak-dependence Model

Superflow processor

Superflow Processor Proposal

Multiscalar Processors

Multiscalar mode of execution

Multiscalar processor

Multiscalar, Trace and Speculative Multithreaded Processors

Additional utilization of more coarse-grained parallelism

Shared memory candidates for CMPs

Shared memory candidates for CMPs

Hydra: A Single-Chip Multiprocessor

Shared memory candidates for CMPs

Motivation for Processor-in-Memory

PIM or Intelligent RAM (IRAM)

PIM Challenges

Conclusions on CMP

Motivation for Multithreaded Processors

Multithreading

Multithreaded Processors

Approaches of Multithreaded Processors

Comparision of Multithreading with Non-Multithreading Approaches

Simultaneous Multithreading (SMT) and Chip Multiprocessors (CMP)

Simultaneous Multithreading

Combining SMT and Multimedia

The SMT Multimedia Processr Model

IPC of Maximum Processor Models

CMP or SMT?

This is the End!

Author: Jurij Silc

Email: Jurij.Silc@ijs.si

Home Page: http://www-csd.ijs.si/silc

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