An instruction is then said to be dispatched from a reservation station to the FU when all operands are available, and execution starts.
If all its operands are available during issue and the FU is not busy, an instruction is immediately dispatched, starting execution in the next cycle after the issue.
So, the dispatch is usually not a pipeline stage.
An issued instruction may stay in the reservation station for zero to several cycles.
Dispatch and execution is performed out of program order.
Other authors interchange the meaning of issue and dispatch or use different semantic.