Architectural Challenges and Implications
Preserve object code compatibility (may be avoided by a virtual machine that targets run-time ISAs)
Find ways of expressing and exposing more parallelism to the processor. It is doubtful if enough ILP is available. Harness thread-level paralelism (TLP) additionally.
Power consumption for mobile computers and appliances.
Soft errors by cosmic rays of gamma radiation may be faced with fault-tolerant design through the chip.