M. Wegrzyn, F. Novak, A. Biasizzo, M. Renovell.
Functional testing of processor cores in FPGA-based applications.
Computing and Informatics, Vol. 28, No. 1, 2009, pp. 97-113.
Embedded processor cores, which are widely used in SRAM-based
FPGA applications, are candidates for SEU-induced (Single Event Upset) faults
and need to be tested occasionally during system exploitation. Verifying a proces-
sor core is a difficult task, due to its complexity and the lack of user knowledge about
the core-implementation details. In user applications, processor cores are normally
tested by executing some kind of functional test in which the individual processorís
instructions are tested with a set of deterministic test patterns, and the results are
then compared with the stored reference values. For practical reasons the number
of test patterns and corresponding results is usually small, which inherently leads
to low fault coverage. In this paper we develop a concept that combines the whole
instruction-set test into a compact test sequence, which can then be repeated with
different input test patterns. This considerably improves the fault coverage with no
additional memory requirements.