F. Novak, P. Mrak, A. Biasizzo.
Test strategies for embedded ADC cores in a system-on-chip : a case study.
Computing and Informatics, Vol. 31, No. 2, 2012, pp. 411-426.
Testing of a deeply embedded mixed-signal core in a System-on-Chip
(SoC) is a challenging issue due to the communication bottleneck in accessing the
core from external automatic test equipment. Consequently, in many cases the
preferred approach is built-in self-test (BIST), where the major part of test activity
is performed within the unit-under-test and only final results are communicated
to the external tester. IEEE Standard 1500 provides efficient test infrastructure
for testing digital cores however, its applications in mixed-signal core test remain
an open issue. In this paper we address the problem of implementing BIST of a
mixed-signal core in a IEEE Std 1500 test wrapper and discuss advantages and
drawbacks of different test strategies. While the case study is focused on histogram
based test of ADC, test strategies of other types of mixed-signal cores related to
trade-off between performance (i.e., test time) and required resources are likely to
follow similar conclusions.