Implementation of security extension for IEEE Std. 1149.1 and analysis of possible attack scenarios,
Informal digest of papers, 12th IEEE European Test Symposium, ETS'07, pp. 223-227, Freiburg, Germany, May 20-24, 2007.
The paper addresses the security problems of boundary-scan design and investigates currently proposed solutions.
Recently proposed security extension for IEEE Std. 1149.1 providing a locking mechanism is discussed.
Possible attack scenarios are analysed. Complete attack time is calculated for different lengths
of Key/Lock registers. For a large length of the Key/Lock registers it is practically impossible
to perform a complete attack. Assuming that the attacker has some limited time interval to perform the attack,
the probability of compromising the system is explored and the probability of successful attack
within a given time interval is calculated. Test Access Port control logic with locking mechanism was
implemented in Xilinx Spartan3 FPGA. The mechanism requires small hardware overhead and can be easily
included in the IEEE Std 1149.1 test infrastructure.